In recent years, a frequency synthesizer with a high-speed lockup operation has been sought for cellular telephones, etc. Code 101 in FIG. 6 is an example of a frequency synthesizer of the conventional technology and is provided within a semiconductor device which composes the transmitting/receiving circuit of a cellular telephone.
This frequency synthesizer 101 has oscillator 131, frequency divider 132, clock signal generator 133, phase comparator 134, charge pump circuit 135, low-pass filter 136, voltage generating circuit 137, fractional frequency division control circuit 138, and ripple correcting circuit 139.
Charge pump 135 outputs control signal to oscillator 131 via low-pass filter 136 and oscillator 131 outputs external output signal (OUT) with a frequency complying with the input control signal to frequency divider 132 and other circuits within the semiconductor device provided with said frequency synthesizer 101.
Frequency divider 132 controls the frequency division value according to fractional frequency division control circuit 138; external output signal (OUT) input to frequency divider 132 is frequency divided according to the frequency division value, and output to phase comparator 134 as a comparison signal.
The frequency divided signal and reference clock signal output by clock signal generator 133 are input to phase comparator 134, and phase comparator 134 compares the phase and outputs the comparison result to charge pump circuit 135.
Charge pump circuit 135 outputs a control signal to oscillator 131 via low-pass filter 136 and, as a result, oscillator 131 changes the frequency of external output signal (OUT) according to the input control signal, and the comparison signal is brought in phase with the reference clock signal. Incidentally, the channel interval is set, for example, at 25 kHz or 12.5 kHz with 900 MHz as the reference frequency in a cellular telephone. Therefore, it is necessary to create an external output signal (OUT) with 12.5 kHz or 25 kHz intervals with 900 MHz as the reference frequency to yield 900.025 MHz, 900.050 MHz, . . . , etc.
On the other hand, the reference clock signal must have a high frequency in order to make the response speed fast. Therefore, in aforementioned frequency synthesizer 101, fractional frequency division control circuit 138 changes the frequency division value of frequency divider 132 cyclically so that the frequency of external output signal (OUT) is equal to the frequency of the reference clock signal multiplied with the average frequency division value.
For example, when using a reference clock signal with a frequency of 225 kHz, if the frequency division value of frequency divider 132 is 4000 during 8 cycles of the reference clock signal and 4001 only during the next cycle, the average frequency value which averaged one cycle of frequency division value change (9 cycles of reference clock signal) becomes 4000+1/9 and the frequency of the external output signal (OUT) becomes 900.025 MHz from 225 kHz.times.(4000+1/9 )=900.025 MHz.
Also, if the frequency division value during the second cycle of the reference clock signal is 4001 and the remaining 7 cycles is 4000, the average frequency division value becomes 4000+2/9 and the frequency of external output signal (OUT) becomes 900.050 MHz. By thus changing the frequency division value cyclically, external output signal (OUT) of the necessary frequency can be obtained from a reference clock signal of relatively high frequency.
However, when changing the frequency division value cyclically as described above, the phase of the comparison signal continues to change cyclically even after external output signal (OUT) has been locked up and the comparison signal and the reference clock signal are out of phase.
Therefore, a signal complying with the phase shift is output from phase comparator 134 and ripple current of a charge value complying with the phase shift continues to be output from charge pump circuit 135. Codes (A.sub.1) to (A.sub.8) in FIG. 7 are examples of ripple current and if the magnitude of ripple current (A.sub.4) is taken as the minimum unit, each ripple current (A.sub.1) to (A.sub.8) is respectively 7 times, 5 times, 3 times, 1 times, -1 times, -3 times, -5 times, and -7 times the minimum unit.
This type of ripple current generates spurious components in external output signal (OUT). And, in addition to adversely affecting the receiving characteristics of communication equipment such as cellular telephone, etc., it creates problems during transmission, which is disadvantageous.
Therefore, a countermeasure is used even in said frequency synthesizer 101 of the conventional technology, and voltage generating circuit 137 and ripple correcting circuit 139 are provided. This ripple correcting circuit 139 has plural capacitors 141 and switches 142 that connect capacitors 141 to voltage generating circuit 137 and is designed so that fractional frequency division control circuit 138 selects capacitor 141 according to the magnitude of the ripple current, closes switch 142, and connects the corresponding capacitor 141 to voltage generating circuit 137.
Then, when switch 142 is closed and reference voltage output by voltage generating circuit 137 is applied to selected capacitor 141, compensation current of equal magnitude is formed with opposite polarity to the ripple current. This compensation current is indicated by codes (B.sub.1) to (B.sub.8) in FIG. 7. When compensation currents (B.sub.1) to (B.sub.8) are superimposed on the output of charge pump circuit 135, ripple currents (A.sub.1) to (A.sub.8) are cancelled.
However, even if an attempt is made to cancel the ripple current by forming a compensation current of equal charge value with opposite polarity that the ripple current, the magnitude of the ripple current is changed by the characteristic fluctuation in charge pump circuit 135 and temperature fluctuation, so that canceling the ripple current accurately with the compensation current is difficult. Therefore, there is the problem of not being able to completely eliminate the spurious components contained in external output signal (OUT).
The present invention was designed to solve said drawbacks of the conventional technology and its objective is to provide a frequency synthesizer of favorable characteristics in which spurious components are not included in the output signals.